Electronic display devices, such as liquid crystal (LC) displays and organic light-emitting diode (OLED) displays, are becoming common and even preferred over older cathode-ray displays, as a result of the electronic displays' thinness, reduced weight, and reduced power consumption relative to older displays. They have also allowed the development of larger area displays. This has led to a demand for even larger displays, e.g. for televisions. However, manufacturing difficulties with larger displays means that the cost of making a display of this sort increases rapidly with the size.
Electronic displays are commonly manufactured by providing control circuitry (e.g. a pattern of thin-film transistors, or TFTs, which can comprise one or several layers) and light-emitting materials on a substrate, such as a sheet of glass. Other materials can be provided as well, such as patterned color filters, or layers of liquid crystals in LC displays. Such displays require multiple coating and patterning steps to achieve the final product.
As the display size increases, such processes become more difficult. One problem is that as the display is made larger, the apparatus necessary for the coating and patterning steps also becomes larger and more expensive, and requires greater area, often in a cleanroom, which adds further expense. In addition, a defect in manufacturing that makes a display unusable is more expensive, because it involves the loss of a larger, more expensive substrate. A defect rate that would be acceptable for a small display can be intolerable for a much larger display. This can lead to tighter controls in manufacturing, which also adds to the cost.
One approach to improve manufacturability of large displays has been to produce smaller display units which are then joined together in a tiled display. Examples include U.S. Pat. Nos. 5,661,531; 5,056,893; 5,673,091; and 5,903,328. While attractive for ease of manufacturing, tiled displays create other problems, such as access to proper control of image display. To properly display images, electronic displays require data and control signals present in two dimensions, e.g. data signals on column connections and control signals present on row connections. In a 2×2 array of rectangular tiles, each of the tiles has one edge exposed in each dimension, allowing such connections, for example as shown in FIG. 1A of U.S. Pat. No. 5,903,328. However, connecting a tiled array in this manner doubles the necessary connections to control the display, when compared to a single-unit display. Further, for large arrays requiring more than a 2×2 array of tiles (for example 2×3), this method of edge connection is not feasible, as some of the tiles will only have one side, or even no sides, exposed.
Brody et al., in US Patent Application 2006/0044215 A1, teach a method of overcoming this limitation in which tiles can be overlapped to create larger displays. A disadvantage of this method, however, is that the tiles must now include tile-to-tile connections. This requirement necessarily increases the complexity and difficulty of manufacturing each tile.
U.S. Pat. No. 5,889,568 describes various approaches for making tiled displays having larger numbers of tiles. For example, each tile may be formed as a module and connected on at least two edges (for example a row edge and a column edge). Alternately, tile to tile connections can be formed. Since space for the connections to the tiles and sealing of the tiles must be hidden between emitting pixel areas, this approach is only valid for displays with very large pixel sizes or low resolution.
Boisdron et al., in U.S. Pat. No. 5,673,091, teach methods to reduce or hide the space required for the seal regions of the tiles and the electrical connections to the tiles or between the tiles within the display area in an effort to improve display quality. However these methods add expense and manufacturing complexity.
Cok, in U.S. Pat. No. 6,999,045, teaches that the display file elements can be connected in series or parallel. However, within-tile communications are handled in a conventional manner, thereby limiting the maximum size of a single tile. Furthermore this approach still requires hiding the tile-to-tile electrical connections or seal regions within the display, such as by optical wave guide, for tiled arrays greater than 2×2.
Matsumura et al., in US 2006/0055864 A1, teach a method for the assembly of a display using semiconductor ICs affixed within the display for controlling pixel elements where the embedded transistors in the ICs replace the normal functions performed by the TFTs of prior art displays. The device of Matsumura et al. is driven by a conventional orthogonal array of row-control wires and column data wires, and as such does not facilitate tiling or the fabrication of long or large displays.
The goal of tiling multiple smaller displays remains desirable for production of large-area, low-cost displays. Thus, despite the advances in manufacturing larger tiled displays, there remains a need for improved large displays with greater ease of manufacturing.